Investigating Effects of Wrong-path Memory References in Shared-memory Multiprocessors by Ayse Yilmazer a Dissertation Submitted in Partial Fulfillment of the Requirements for the Degree of Master of Science in Electrical and Computer Engineering University of Rhode Island

High-performance multiprocessor systems are built around out-oforder processors with aggressive branch predictors. Despite their relatively high branch prediction accuracies, these processors execute many memory instructions on mispredicted paths. Previous studies that focused on uniprocessors systems showed that these wrong-path memory references may pollute the caches by bringing in data that are not needed on the correct execution path and by evicting useful data or instructions. Additionally, they may also increase the amount of cache and memory traffic. On the positive side, however, they may have a prefetching effect for memory references on the correct path. For multiprocessor systems, the performance implications of these wrong-path memory references are more widespread, including, but not limited to, more cache-to-cache transfers, write-backs, and cache block state transitions. In this thesis, we investigated the effects of wrong path memory references on the memory system behavior of multiprocessors systems including both broadcast and directory-based cache coherent Shared Memory Multiprocessor systems (SMPs) and Multiple Chip Multiprocessor systems (multi-CMPs). Our results showed that these wrong-path memory references can increase the amount of cache-to-cache transfers by 32%, invalidations by 8% and 20% for broadcast and directory based SMPs, respectively, and the number of writebacks by up to 67% for both systems. In addition to the extra coherence traffic, wrong-path memory references also increase the number of cache block state transitions by 21%and 32% for broadcast and directory-based SMPs, respectively. On multi-CMPs, wrong-path memory references increase L1 and L2 cache traffic by 16% and 35% and the traffic on the internal and external networks by 36% and 30%, respectively. In addition to their prefetching and pollution effects, these additional L1 and L2 cache replacements result in additional writebacks (up to 70%) and L1 copy invalidations (up to 68%), both of which subsequently increase the coherence traffic in both the internal and external networks and they cause 4% and 16% extra cache block state transitions on L1 and L2 caches, respectively in multi-CMPs. In order to reduce the performance impact of these wrong-path memory references, we introduce two simple mechanisms – filtering wrong-path blocks that are not likely-to-be-used and wrong-path aware cache replacement – that yield speedups of up to 37% for SMPs and 52% for multi-CMPs.